It is known in the digital data processing art to provide multiple processing units and to overlap the operation thereof, so that instruction execution is conducted by the processing units working in parallel in a "pipelined" fashion. For example, one processing unit may be used to fetch instructions to be processed, and a second processing unit may be used to execute the instructions. The overall processing time is shortened, since the first processing unit is already fetching the next instruction while the second processing unit is executing the previous instruction.
It is also known in the digital data processing art to shorten the processor cycle time, defined as the time required by the processor to execute a given instruction, by providing a relatively low capacity, fast cycle time memory (known as a "cache memory") between the processor and the relatively high capacity, slow cycle time main memory. During the "fetch" portion of the instruction execution cycle, the processor first checks the cache memory to see whether the desired information resides in it. If it does, the processor is able to access the information faster than if it had to access the main memory. If the information is not contained within the cache memory, then a block of information stored in the main memory, including the information being fetched by the processor, is stored into the cache memory, since there is a relatively high probability that subsequent memory accesses will be to information stored in such block. The condition in which the information requested by the processor is found within the cache is called a cache "hit", and the opposite condition is called a cache "miss".
The present invention provides a high performance digital processing system achieving a relatively short processor cycle time, by providing a pair of pipelined processors, one for fetching instructions, the other for executing the instructions, and providing a high speed cache memory for use by each processor. Under virtually all conditions the cache memory associated with each processor is accessible by such processor at any time and independently of the operation of the other processor and its associated cache memory.